The invention relates to high power semiconductor switches, and more particularly to FET switch layouts and biasing thereof.
In modern RF communication systems, a semiconductor-based transmit-receive switch is often the last/first component encountered by a transmitted/received signal before/after encountering an antenna.
Many of the main advances in semiconductor-based transmit-receive switches have been with respect to isolation and insertion loss. Groups of FETs are arranged in the switch along with judiciously chosen resistors and capacitors to ensure low insertion loss along the signal path and high isolation from the off paths. One general approach utilizes, instead of a single FET switch along each alternative path, a group of FET switches in series. This general approach moreover does not simply turn the FETs on and off by utilizing only a voltage at the gate, but instead biases both the gate and the source/drain in a forward and reverse manner to turn the FETs full-on and full-off respectively. Two general approaches have been used to enable this, namely, the use of negative voltage sources, and the use of DC blocking capacitors.
In both known approaches n-FETs are used due to their lower insertion loss and low harmonics while p-FETs are avoided due to their higher insertion loss caused in part by the relative low mobility of holes in a p-FET compared with the relatively higher electron mobility in an n-FET. The FETs described herein are MOSFETs which include a gate, a source, a drain and a backgate. For n-FETs which are nMOSFETs as depicted in FIGS. 1A and 1B, in order for the transistor to be fully on, the voltage applied to the backgate should be the substantially similar to that applied to the source and the drain, while the voltage at the gate must be higher, in the case of silicon on insulator (SOI), than the voltage at the source or drain by 2.5V. In order for the SOI n-FET to be properly off, the voltage at the backgate should be less than the voltage at the drain and the source, and the voltage at the gate should be less than the voltage at the drain or the source. Harmonic generation occurs when the depletion region of the parasitic diodes associated with the n-FET devices are modulated by a signal when it passes through the n-FET.
An example of a known series-shunt switch 100 according to a prior art approach utilizing negative voltage sources for biasing is presented in FIG. 1A. An RF terminal 101 is coupled along a signal or series path 111 through a series FET group switch 110 to an antenna 102, and is connected along a shunt path 121 through a shunt FET group switch 120 to ground 103. Each FET group switch 110, 120 has a group of n-FET transistors connected in series with the respective path from the RF terminal 101 to the antenna 102 or from the RF terminal 101 to ground 103. Each FET group switch 110, 120 also has a respective associated group of source/drain resistors 115, 125, each resistor of which is coupled to a sources and drain of a respective FET of the group switch it is associated with.
The gates of the FETs of the series FET group switch 110 are biased by a series gate biasing terminal 112 with a voltage VgSERIES, while gates of the FETs of the shunt FET group switch 120 are biased by a shunt gate biasing terminal 122 with a voltage VgSHUNT. The backgates of the FETs of the series FET group switch 110 are biased by a series backgate biasing terminal 114 with a voltage VbSERIES, while backgates of the FETs of the shunt FET group switch 120 are biased by a shunt backgate biasing terminal 124 with a voltage VbSHUNT. All of the sources and drains of the series FET group switch are effectively biased at the same DC voltage level of the RF terminal 101, ground 103, and the antenna 102 which is 0.0V.
To connect the RF terminal 101 to the antenna 102 and put the switch 100 into series mode, the series gate biasing terminal 112 is set to VgSERIES=2.5V, while the series backgate biasing terminal 114 is set to VbSERIES=0.0V, and while the shunt gate bias terminal 122 and the shunt backgate bias terminal 124 are each set to VgSHUNT=VbSHUNT=−2.5V with use of a negative voltage source (not shown) which typically would be an on-chip negative voltage generator. Setting the biases in this manner ensures that the FETs of the series FET group switch 110 are fully on while the FETs of the shunt FET group switch 120 are properly off, within the reliability/breakdown limits of operation.
To connect the RF terminal 101 to ground 103 and put the switch 100 into shunt mode, the series gate biasing terminal 112 and the series backgate biasing terminal 114 are set to VgSERIES=VbSERIES=−2.5V with use of the negative voltage source, while the shunt gate biasing terminal 122 is set to VgsHUNT=2.5V, and while the shunt backgate bias terminal 124 is set to VbSHUNT=0.0V. Setting the biases in this manner ensures that the FETs of the series FET group switch 110 are properly off while the FETs of the shunt FET group switch 120 are fully on, within the reliability/breakdown limits of operation.
This configuration biases each FET group switch in the forward or the reverse direction ensuring respectively low insertion loss and high isolation which are very important when dealing with high-power signal transmission.
Some of the drawbacks of the series shunt switch 100 of FIG. 1A are that it requires oscillators, charge pump circuitry, positive and negative voltage regulators, supply filtering including a negative supply filter which usually occupies a much larger area than a positive supply filter, and a pseudo-random bit sequence (PRBS) generator. The additional components can create noise, spurious tones, and spurious spectral emissions and tend to occupy a large percentage of IC (integrated chip) die area, and consume extra DC power.
Another example of a known series-shunt switch 150, this one according to a prior art approach utilizing DC blocking capacitors is presented in FIG. 1B. An RF terminal 151 is coupled along a series path 161 to a first blocking capacitor 181 coupled in series with a series FET group switch 160 in turn coupled in series with a second blocking capacitor 182 to an antenna 152, and is connected along a shunt path 171 to a third blocking capacitor 183 coupled in series with a shunt FET group switch 170 in turn coupled in series with a fourth blocking capacitor 184 to ground 153. Each FET group switch 160, 170 has a group of n-FET transistors connected in series with the respective path from the RF terminal 151 to the antenna 152 or from the RF terminal 151 to ground 153. Each FET group switch 160, 170 also has a respective associated group of source/drain resistors 165, 175. Each FET of the series and shunt FET group switches 160, 170 has a respective resistor of its associated group of source/drain resistors 165 coupled across its source and drain. All of the sources and drains of the FETs of the series FET group switch 160 are supplied with a series source/drain bias Vs/dSERIES from a series source/drain biasing terminal 166. All of the sources and drains of the FETs of the shunt FET group switch 170 are supplied with a shunt source/drain bias Vs/dSHUNT from a shunt source/drain biasing terminal 176. The actual mechanism for providing the biasing to the source/drains may be chosen from any number of known methods for providing biasing voltage. For the purposes of the switching function described herein, the chosen level of the biasing applied at each of the source/drains is the important factor.
The gates of the FETs of the series FET group switch 160 are biased by a series gate biasing terminal 162 with a voltage VgSERIES, while gates of the FETs of the shunt FET group switch 170 are biased by a shunt gate biasing terminal 172 with a voltage VgSHUNT. The backgates of the FETs of the series FET group switch 160 are biased by a series backgate biasing terminal 164 with a voltage VbSERIES, while backgates of the FETs of the shunt FET group switch 170 are biased by a shunt backgate biasing terminal 174 with a voltage VbSHUNT.
To connect the RF terminal 151 to the antenna 152 and put the switch 150 into series mode, the series gate biasing terminal 162 and the shunt source/drain bias terminal 176 are set to VgSERIES=Vs/dHUNT=2.5V, while the series backgate biasing terminal 164, the shunt backgate biasing terminal 174, the series source/drain bias terminal 166 and the shunt gate bias terminal 172 are set to VbSERIES=VbSHUNT=Vs/dSERIES=VgSHUNT=0.0V. Setting the biases in this manner ensures that the FETs of the series FET group switch 160 are fully on while the FETs of the shunt FET group switch 170 are properly off, within the reliability/breakdown limits of operation. In this mode of the series-shunt switch's 150 operation, the third blocking capacitor 183 blocks the RF terminal 151 from the 2.5 V DC shunt source/drain biasing, while the fourth blocking capacitor 184 blocks the 2.5 V DC shunt source/drain biasing from ground 153.
To connect the RF terminal 151 to ground 153, and put the switch 150 into shunt mode, the shunt gate biasing terminal 172 and the series source/drain bias terminal 166 are set to VgSHUNT=Vs/dSERIES=2.5V, while the shunt backgate biasing terminal 174, the series backgate biasing terminal 164, the shunt source/drain bias terminal 176 and the series gate bias terminal 162 are set to VbSHUNT=VbSERIES=Vs/dSHUNT=VgSERIES=0.0V. Setting the biases in this manner ensures that the FETs of the shunt FET group switch 170 are fully on while the FETs of the series FET group switch 160 are fully off, within the reliability/breakdown limits of operation. In this mode of the series-shunt switch's 150 operation, the first blocking capacitor 181 blocks the RF terminal 151 from the 2.5 V DC series source/drain biasing, while the second blocking capacitor 182 blocks the 2.5 V DC series source/drain biasing from the antenna 102.
As with the circuit depicted in FIG. 1A, this configuration biases each FET group switch in the forward or the reverse direction ensuring respectively low insertion loss and high isolation without the use of negative voltage generators.
Some of the drawbacks of the series-shunt switch 150 of FIG. 1B are that it often requires a DC-DC boost converter circuit (not shown), and requires that all terminals be blocked with an appropriately sized blocking capacitor in order to ensure flexible voltage settings. Integrated DC blocking capacitor's take up significant IC die area and may easily be damaged during ESD (ElectroStatic Discharge) events hampering the reliability and robustness of the circuit. Use of off chip capacitors also occupies a significant board area and can add significant cost. Although the blocking capacitors 181, 182, 183, 184, are effective in allowing all of the bias voltages to be positive and present a tolerable insertion loss, their use does, however, cause the switch 150 of FIG. 1B to exhibit more insertion loss than the switch 100 of FIG. 1A.